1. Technical Field
The present disclosure is directed to systems and methods for active clock deskew and, more particularly, to systems and methods for achieving desirable clock deskew at reduced power levels. The disclosed systems/methods employ a resistance-based distributed clock deskew technique that has broad commercial/industrial applicability, e.g., in VLSI/ULSI chips, such as microprocessors, digital signal processing systems (DSPs), integrated circuits, application-specific integrated circuits (ASICs), micro-controllers, embedded systems, memory chips and the like.
2. Background Art
Semiconductor technology scaling enables tremendous advances in developing high-speed, very large scale integration (VLSI) chips. However, with semiconductor technology being scaled into smaller feature sizes, timing noise such as clock skew is exacerbated by the growing chip complexity. Timing noise/clock skew is caused by increasingly large process variations. Large process variations imply and/or translate to less control of device parameters and result in large uncertainty in clock propagation delay.
As used herein, clock skew is defined as the difference in time between simultaneous clock transitions within a VLSI chip (or other processor). There are several factors that contribute to clock skew. Increased levels of chip complexity generally require clock signals to be distributed across large die area and to drive huge load capacitance. Due to such factors, clock signals are more likely subject to design mismatches. In state-of-the-art microprocessors, clock skew is consuming a large percent of the total cycle time, thereby limiting the microprocessor to logic computations for only part of the total cycle time. Clock skew as a fraction of the ever shrinking cycle time is expected to increase as technology is scaled further. This directly affects the maximum achievable performance, reliability, and power dissipation in a variety of applications, e.g., high-performance synchronous VLSI/ULSI chips.
The 2003 International Technology Roadmap for Semiconductor (ITRS) has identified design robustness as one of the “Grand Challenges” in the next decade. Clock skew is a critical factor that may ultimately determine the design robustness in future VLSI chips. Consistent with the importance of clock skew to performance, clock deskew techniques have been developed for high-performance VLSI design. The basic prior art approach to clock deskew involves intentional introduction of time delay in the opposite direction of clock skew, on different clock distribution paths, to offset any skew on these paths. Existing approaches achieve clock deskew by introducing additional capacitance into VLSI chips. However, the dynamic power dissipation of a VLSI chip, which is the dominant power component, is a linearly increasing function of chip capacitance. As a result, the existing clock deskew circuits incur large power overheads because clock signals switch the added capacitance constantly, thereby significantly increasing total chip power dissipation and severely affecting chip performance.
Clock deskew techniques have been effective in practice and have been applied extensively in high-performance VLSI chips. While the existing clock deskew techniques are effective in minimizing clock skew, the power dissipation incurred by these techniques is significant. In state-of-the-art microprocessors, a large percent of total chip power is contributed to clock generation and the associated distribution network. Power dissipation associated with the clock network is moving in an unmanageable direction, requiring enhanced techniques to control increasingly severe clock skew issues. Indeed, the combination of clock skew and clock-related power consumption challenge the very foundation of the low power and cost benefits of VLSI chips.
Accordingly, a need exists for clock deskew systems and methods that reduce and control clock skew, while requiring reduced levels of power consumption. These and other objects are satisfied by the systems and methods disclosed herein.